Semiconductor manufacturing is the process of transforming r...
Semiconductor manufacturing is the process of transforming raw silicon wafers into highly integrated circuits capable of processing and storing data. At its core, it involves a series of complex physical and chemical steps that imprint circuit patterns onto a wafer substrate to eventually form functional semiconductor devices.
This blog will bring you a comprehensive introduction of semiconductor wafer manufacturing process, and go into details of technologies used in chip manufacturing, applications and the machine used.
However, it is hard to understand what it really is only by concept.
In simple words, semiconductor manufacturing is generally understood as chip manufacturing, but to be more serious, there is a fine line between semiconductor manufacturing and chip manufacturing.
Chip Manufacturing = IC Design + Wafer Manufacturing (also called semiconductor fabrication) + Packaging & Testing
Thus in concept, semiconductor manufacturing is the wafer manufacturing in the process of chip manufacturing , which also answers the question of “What is semiconductor device fabrication?” from a simple angle.
But what about the processes of semiconductor device fabrication? The following content will give a full explanation.
Chip manufacturing can use various process technologies, including CMOS, as well as BiCMOS, GaAs, FinFET, SOI, and others.
Generally, Semiconductor manufacturing includes 4 major fabrication stages. The 4 major stages can be divided into 35 sub stations(11+6+9+9). Going deeper, the 35 sub stations can be divided into detailed 200+ process steps.
The 35 stations that this blog going to explain is mainly focused on the CMOS process route.
Why CMOS?
CMOS (Complementary Metal-Oxide-Semiconductor) technology is currently the most widely used semiconductor manufacturing process, mainly due to the following reasons:
●Low Power Consumption: CMOS structures effectively reduce static power consumption, making them especially suitable for large-scale integrated circuits such as microprocessors and memory devices.
●High Integration Density: CMOS processes support extremely high transistor densities, enabling the realization of complex circuits.
●Mature and Stable: After decades of development, CMOS technology is highly mature, with well-established fabrication equipment and design methodologies.
●Strong Compatibility: CMOS processes integrate well with various back-end processes (such as multi-level metal interconnects and packaging) and offer relatively low production costs.
●Wide Application: CMOS chips are extensively used in smartphones,computers, servers, IoT devices, automotive electronics, and many other fields.
In contrast, technologies like BiCMOS and GaAs offer specific advantages (such as high frequency, high speed, and mixed-signal capabilities) but involve higher costs and more complex processes, making them less suitable for large-scale digital chip production.
FinFET and SOI can be considered "advanced" or "variant" forms of CMOS technology designed to meet the performance and power requirements of more advanced technology nodes. They still fall under the CMOS technology umbrella but feature more sophisticated structures and processes.
In summary:
CMOS is the mainstream and most widely applied technology in modern semiconductor chip manufacturing.
Before going through each step, we should get to know how many components are in a single chip.
Chip has 7 sectors as following listed, and semiconductor parts are the transistor, logic gates / logic circuits and memory cells
1.Transistor: Like a switch, control current passing through, is the chip's smallest unit
2.Logic Gate/ Logic Cell: Small module composed of transistors used for logical operations such as addition and subtraction judgments
3.Memory Cell: Data Storage
4.Interconnect: Connect the various parts
5.l/O Interface: The channel that allows the chip to communicate with the outside world, such as by connecting the keyboard, screen, etc
6.Clock Circuit: Like a metronome, it makes all the parts work together in rhythm
7.Packaging: Like the chip“Shell” and“Armor” to protect the internal circuit is not damaged
In semiconductor manufacturing, FEOL (Front-End of Line) refers to all process steps starting from a bare silicon wafer up to the point before forming basic transistor structures (like NMOS/PMOS). FEOL primarily focuses on building the transistor structures, which serve as the foundation of the chip's performance.
There are 11 sub stations FEOL wafer processing as below:
- Material Preparation: Silicon ingots or raw semiconductor substrates, output mirror-polished bare silicon wafers.
- Wafer Cleaning: Input bare wafer material with dust, output clean wafer
- Oxidation: Input clean wafer, output with a layer of thermally grown SiO2(thermal oxide layer) formed on the surface
- STI Isolation Formation: Input wafer with SiO2 or thermal oxide layer, after this station, the wafer had planarized surfaces with STI structures (Shallow Trench Isolation)
- Film Deposition: Input STI wafer, output wafer covered with a functional thin film on surface (covered with polysilicon gate/ dielectric layers), etc.
- Etch Stop / Hardmask Deposition: Input wafer with thin film, output wafer coated with etch-stop or hardmask layers (e.g., SiN, SiCN) for precise pattern control in later steps.
- Gate Patterning: Input wafer with hardmask layer, output wafer with physical gate structure (photoresist removed)
- Ion Implantation: Input wafer with gate structure, output wafer with doping source/drain region
- Rapid Thermal Annealing: Input wafer with doping source/drain region, output lattice repaired and doped activated wafers
- Silicide Formation: Input Post-RTA wafer, output source/drain/gate covered silicon wafer with low resistance metal silicide (Nisi/Tisi2)
- CMP(Chemical Mechanical Polishing): Input wafers that may have multiple stacked, uneven structures on the surface, output wafer whose surface is polished to a highly flat structure (e. g. STI area).
Meol is the key bridge between the front-end transistor structure (FEOL) and the back-end metal interconnect (Beol). The purpose of this stage is to do 3 things:
●Establish a reliable contact between the transistor and the wire;
●Control contact resistance and parasitic effect;
●Keep the structure flat, to lay the foundation for BEOL metallization
To meet this aim, there are 6 sub-stations in MEOL as bellow:
- Contact Hole Etchl: Input planarized wafer with completed transistor structures, output wafer with etched CA (Source/Drain Contact) and CB (Gate Contact) holes, exposing transistor terminals.
- Barrier Layer Deposition: Input wafer with etched contact holes, output wafer with contact holes conformally covered by TiN/TaN barrier layer.
- Metal Fill (Contact Plug): Input wafer with barrier-lined contact holes, output wafer with tungsten-filled CA/CB holes forming contact plugs → Constituting Local Interconnect Layer (M0)
- Contact Resistance Optimization: Input wafer with metal-filled contact plugs, output Wafer with low-resistance contacts optimized by annealing/silicide interface engineering.
- ILD Deposition (Interlayer Dielectric): Input wafer with optimized metal contact plugs, output wafer with dielectric layer covering Local Interconnect Layer (M0).(MEOL-to-BEOL transitional layer)
- CMP Planarization: input wafer with a non-planar ILD surface, output wafer with a flat dielectric surface ready for BEOL metallization
BEOL is the critical stage in semiconductor manufacturing where multi-level metal interconnects are formed to electrically connect transistors and functional blocks. The key objectives of BEOL are:
●Build multi-level metal interconnect networks for signal and power distribution;
●Minimize resistance, capacitance, and parasitic effects to ensure circuit performance;
●Isolate each metal layer with dielectrics to prevent shorts and crosstalk.
To achieve these goals, BEOL consists of the following 9 sub-stations:
- Dielectric Layer Deposition: Input wafer from MEOL with a planarized surface; output wafer with a deposited dielectric layer used to isolate different metal layers.
- Dual Damascene Patterning：Input Dielectric-coated wafer, output wafer with patterned trenches and vias, defined by photolithography and plasma etching.
- Barrier/Seed Layer Deposition: Input wafer with etched trench/via patterns; output wafer conformal barrier layer (e.g., TaN) and seed layer (e.g., Cu), preparing for electroplating.
- Cu Electroplating: Input barrier/seed wafer, output output non-planarized Cu-filled wafers
- CMP Planarization: Input wafer with overfilled metal features; output wafer with a flat surface achieved by chemical mechanical polishing (CMP), enabling further layer stacking.
- Iterative Metal Stacking: Input single-metal-layer wafer, output multi-level interconnect wafer (M1-MX)
- Passivation Deposition:Input final-metal-layer wafer, output wafer with SiN/SiO₂ passivation (0.5-1μm)
- 3D Integration: Input thinned & passivated wafer, output wafer with TSV/RDL for packaging
- Redistribution Layer (RDL) Preparation: Input wafer with completed metal interconnect stack; output wafer with passivation layers for protection and RDL for final chip packaging and I/O routing.
ATP (Assembly, Test, and Packaging) is the final stage in semiconductor manufacturing, where individual dies are prepared for integration into systems. It ensures mechanical protection, electrical connectivity, and product reliability before delivery. The primary goals of ATP are:
●Protect the die mechanically and thermally during operation;
●Provide standardized electrical interfaces for system integration;
●Screen out defective units through electrical testing and ensure long-term reliability.
To achieve these goals, ATP includes the following 9 sub-stations:
- Wafer Sort(CP Test): Input completed wafer, output wafer qualified chips (ink dot/ electronic drawing)
- Wafer Backgrinding: Input tested wafer (post-CP test), output thinned wafer, typically reduced to 100–200 μm thickness to prepare for dicing and final packaging
- Dicing: Individual dies and package substrates/lead frames, output unit where each die is securely attached to the package base using conductive adhesive (epoxy) or solder
- Die Attach: Input wafer and package substrates/lead frames; output a unit where each wafer is securely attached to the package base using conductive adhesive or solder.
- Wire Bonding / Flip-Chip Interconnect: Input die-attached packages; output electrically connected dies via wire bonding (Au/Al wires) or flip-chip solder bumps to the substrate.
- Encapsulation / Molding: Input connected die-package assemblies; output units protected by a molded epoxy or plastic compound, ensuring mechanical and environmental protection.
- Final Test: Input fully assembled packages; output electrically tested units, screened for functional defects using automated test equipment (ATE). This includes parametric, functional, and burn-in testing.
- Marking: Input passed/tested devices; output labeled semiconductor device.
- Tape and Reel / Tray Packaging for Shipment: Input labeled chip, output final chip packages for shipment
Silicon ingots or raw semiconductor substrates, output mirror-polished bare silicon wafers
Description
Transforms high-purity polysilicon into mirror-finished silicon wafers through crystal growth, precision slicing, and polishing. Ensures substrate purity (>99.9999999%) and nanoscale surface flatness (Ra <0.2 nm) for downstream processes.
Process Flow
●Crystal Growth: CZ (Czochralski) or FZ (Float-Zone) method: Pulls monocrystalline ingots from molten polysilicon.
●Ingot Slicing: Diamond wire saw cutting: Slices ingots into 775±25 μm wafers.
●Edge Grinding: Laser/mechanical beveling to eliminate micro-cracks and stress.
●Double-Side Polishing: Chemical Mechanical Polishing (CMP): Achieves surface roughness <0.2 nm.
Principle
●Dislocation control: Limits crystal defects (<500/cm²) via controlled cooling.
●Stress reduction: Edge grinding prevents fracture propagation
●Flatness mechanism: CMP combines chemical etching (colloidal silica) and mechanical abrasion for atomic-level smoothness.
Key Consumables
| Material | Specification |
| High-purity polysilicon | ≥99.9999999%, metallic impurities <1 ppb |
| Diamond wire saw blades | 120-200 μm grit, resin-bonded |
| CMP slurry | Colloidal silica (pH 10.5±0.5), oxidizers |
Main Equipment
●CZ furnace: Quartz crucible, RF heating (1,450°C).
●Diamond wire saw: Tension control ±0.1 N, cutting speed 0.5-2 mm/mi .
●CMP polisher: Dual rotating pads (30-60 rpm), downforce 20-50 kPa
Input bare wafer material with dust, output clean wafer
Description
Removes contaminants (particles, organics, metals) via RCA standard cleaning, megasonic assistance, and Marangoni drying. Ensures surface metal ions <10¹⁰ atoms/cm² for defect-free fabrication.
Process Flow
●SC1 Cleaning: Immersion in 1:1:5 (H₂O:NH₄OH:H₂O₂) at 70-80°C for 10 min.
●DI Water Rinsing: Triple counterflow rinse (18 MΩ·cm resistivity).
●SC2 Cleaning: Immersion in 6:1:1 (H₂O:HCl:H₂O₂) at 70°C for 10 min.
●Megasonic Cleaning: 1 MHz acoustic waves for sub-0.2 μm particle removal.
●Marangoni Drying: IPA vapor gradient drying to prevent watermarks.
Principle
●SC1 mechanism:
○Organic removal: H₂O₂ oxidizes hydrocarbons → soluble compounds.
○Particle lift-off: NH₄OH etches SiO₂, undercutting particles.
●SC2 mechanism:
○Metal ion dissolution: HCl forms soluble chlorides (e.g., CuCl₂).
●Megasonic cavitation: Generates microbubbles to dislodge nanoparticles.
Key Consumables
| Chemical/Item | Specification |
| SC1 solution | NH₄OH (27%), H₂O₂ (30%), DI H₂O (1:1:5) |
| SC2 solution | HCl (37%), H₂O₂ (30%), DI H₂O (6:1:1) |
| Ultrapure DI water | Resistivity ≥18 MΩ·cm, TOC ≤1 ppb |
| IPA (Isopropyl alcohol) | Purity ≥99.99%, low metal ions |
Main Equipment
●Automated wet bench: Teflon tanks, flow-controlled chemical dispensers.
●Megasonic transducer: 1 MHz frequency, power density 1-5 W/cm².
●Marangoni dryer: IPA vapor injectors, N₂ purge system.
●Particle monitor: In-line laser scattering detector (sensitivity: 0.05 μm)
Input clean wafer, output with a layer of thermally grown SiO2(thermal oxide layer) formed on the surface.
Description
Forms a precisely controlled silicon dioxide (SiO₂) layer on silicon wafers through thermal oxidation, serving as gate dielectrics, isolation barriers, and passivation layers.
Process Flow
●Pre-cleaning: RCA Standard Clean: Removes organic/metallic contaminants to ensure oxidation uniformity.
●Wafer Loading: Automated transfer into quartz boat within oxidation furnace (N₂ purge to prevent contamination).
●Thermal Oxidation:
○Dry Oxidation: Pure O₂ at 800–1,200°C → Dense SiO₂ (0.01–0.1 μm/min, preferred for gate oxides).
○Wet Oxidation: H₂O vapor at 700–1,000°C → Rapid growth (0.1–1μm/min, for field isolation).
○Radical Oxidation: O₂/H₂ plasma → Conformal SiO₂ on 3D structures.
●In-situ Annealing: Post-oxidation N₂/H₂ anneal at 900°C to reduce interface states (Dit).
●Thickness Measurement: Ellipsometry or SEM validation of SiO₂ thickness uniformity (±0.1 nm).
Principle
Deal-Grove Model
Mechanisms:
| Oxidation Type | Chemical Reaction | Interface Quality |
| Dry | Si + O₂ → SiO₂ | Dit < 10¹⁰ cm⁻²eV⁻¹ |
| Wet | Si + 2H₂O → SiO₂ + 2H₂ | Dit ~10¹¹ cm⁻²eV⁻¹ |
| Radical | Si + O⁺ → SiO₂ (plasma-enhanced) | Dit < 5×10⁹ cm⁻²eV⁻¹ |
Key Controls:
○Temperature: ±0.5°C tolerance at 1,000°C.
○Crystal orientation: (111) Si oxidizes 1.7× faster than (100) Si.
Key Consumables
| Material | Specification | Function |
| Ultra-pure oxygen | ≥99.999% (5N), H₂O <0.1 ppm | Dry oxidation reactant |
| Deionized H₂O | Resistivity >18 MΩ·cm, TOC <1 ppb | Wet oxidation source |
| Quartz boat/carrier | Low Na⁺/K⁺, high thermal shock resistance | Wafer support during oxidation |
| Hydrogen peroxide | 30% concentration, metal-free | Radical oxidation plasma precursor |
Main Equipment
●Vertical Diffusion Furnace:
○Temperature range: 600–1,200°C (ramp rate 10°C/min).
○Gas delivery: Mass flow controllers (O₂ accuracy ±1 sccm).
●Rapid Thermal Processor (RTP):
○Flash annealing for ultrathin oxides (<2 nm).
●Plasma-Enhanced CVD System:
○For radical oxidation: RF power 300–500W, pressure 0.1–1 Torr.
●Ellipsometer:
○Wavelength range 190–1,700 nm, thickness resolution 0.01 nm.
Input wafer with SiO2 or thermal oxide layer, after this station, the wafer had planarized surfaces with STI structures (Shallow Trench Isolation)
This is the workstation in a semiconductor factory where tiny electrical "moats" are built between transistors on a silicon chip. Think of it like digging trenches between houses in a neighborhood to prevent fires from spreading.
Description
STI (Shallow Trench Isolation) is a technique to keep billions of microscopic transistors on a chip from interfering with each other electrically. By digging narrow trenches and filling them with "electrical insulation" (silicon dioxide), it creates barriers that stop unwanted current leaks or signal crosstalk. This allows chipmakers to pack transistors closer together, making phones faster and batteries last longer.
Process Flow
●Trench Digging: First, a thin "safety pad" (silicon dioxide layer) is grown on the silicon wafer.Then, a hard "digging mask" (silicon nitride layer) is added. Using light-based patterns (photolithography) and plasma "shovels" (Reactive Ion Etching), trenches are carved into the silicon. These trenches are shallow (0.2–0.5 μm deep) with smooth, angled walls.
●Trench Prep & Lining: Trenches get a thin oxide coating (liner) to repair surface damage and improve insulation. This step prevents oxygen from sneaking into nearby transistors during later processes.
●Filling the Trenches: Trenches are completely filled with liquid insulator (SOD - Spin-On Dielectrics) or gas-deposited oxide (HDP-CVD). SOD acts like "liquid ceramic" that flows into every corner, while HDP-CVD is like spraying insulating foam under high pressure.
●Smoothing the Surface: Excess insulator material bulges above the wafer surface. A "wafer polisher" (CMP machine) grinds it down flat using a special toothpaste-like slurry (cerium oxide-based). The silicon nitride mask acts as a "stop layer" to prevent over-polishing.
●Mask Removal:The silicon nitride mask is stripped away using chemicals, revealing the finished isolation trenches.
How It Works
Imagine building miniature garden walls between electronic components:
●Dig narrow ditches in the silicon "soil".
●Fill them with glass-like insulation (oxide).
●The insulation blocks electrical signals from jumping between neighboring transistors, just like a wall stops weeds from spreading.
Key Benefit: Enables ultra-dense transistor layouts without electrical chaos.
Key Materials (What's Used)
| Material | Function |
| Silicon Dioxide (SiO₂) | afety pad & trench liner - Protects silicon during digging |
| Silicon Nitride (SiN) | Hard digging mask - Acts as a "stop sign" during polishing |
| SOD (Spin-On Dielectrics) | Liquid insulator - Fills trenches like self-leveling epoxy |
| HDP-CVD Oxide | Gas-sprayed insulator - Fills trenches under high pressure |
| Cerium Oxide (CeO₂) Slurry | Polishing paste - Grinds excess oxide flat without scratching |
| NSA/DCA Additives | "Smart chemicals" in slurry - Control polish speed precisely |
Key Equipment (Machines Involved)
●Thermal Oxidation Furnace: Grows the silicon dioxide safety pad (like baking a protective glaze).
●CVD/PECVD Machine: Deposits the silicon nitride hard mask (sprays on a durable coating).
●Photolithography Stepper: Projects light patterns to define trench locations (like a microscopic stencil printer).
●Reactive Ion Etch (RIE) Machine: Plasma etcher that carves trenches with precision (microscopic sandblaster).
●SOD Coater/Developer: Spins liquid SOD into trenches and bakes it solid (like a wafer-sized spin-art machine).
●HDP-CVD System: High-pressure sprayer for oxide trench filling.
●CMP Polisher: Grinding machine with cerium slurry to flatten the surface (nanoscale belt sander).
●Wet Etch Station: Chemical bath to remove silicon nitride mask after polishing.
Input STI wafer, output wafer covered with a functional thin film on surface (covered with polysilicon gate/ dielectric layers), etc.The "Nano-Spray Paint Booth" for Computer Chips
This is where ultra-thin coatings (500x thinner than a human hair) are applied to silicon wafers. Like spray-painting a car but at atomic scale, these layers make chips conduct electricity, block signals, or protect components.
Process Flow (Step-by-Step)
●Wafer Cleaning：Wafers get "ion showered" with argon gas to remove dust/oil so films stick properly.
●Coating Selection:
○Physical Vapor Deposition (PVD)
i.Evaporation: Melt metals (aluminum/tungsten) into vapor that condenses on wafers like steam on a mirror.
ii.Sputtering: Fire ion "bullets" at metal targets to knock atoms onto wafers like microscopic sandblasting.
○Chemical Vapor Deposition (CVD)
i.Pump special gases (e.g., silane) into a chamber, zap with electricity → gas breaks down and "rains" atoms onto wafers.
●Film Treatment: Bake wafers to harden films or blast with plasma to fine- tune properties.
●Quality Check: Laser scanners measure thickness; imperfect layers get dissolved and reapplied.
Working Principle
●PVD = Cooking Spray Method
Heat metal → gas cloud → coats wafer (like non-stick pan coating).
●CVD = Gas LEGO Assembly
Gases chemically react on wafer surface, "building" layer-by-layer like stacking LEGO bricks.
●Uniformity Trick:
Wafers rotate like barbecue rotisserie for even coating.
Key Materials (What’s Consumed)
| Material | Function | Real-World Example |
| Target Metals | PVD"paint cans" (source atoms) | Aluminum ingots (wires) |
| Precursor Gases | CVD "ingredient gases" | Silane (SiH₄) for silicon |
| Reactive Gases | Help films form/harden | Oxygen (makes SiO₂) |
| Etchants | Remove defective films | Hydrofluoric acid (HF) |
Equipment (Tools Used)
●Vacuum Chamber
○Sealed metal tube (air removed) – creates outer-space conditions for clean coating.
●Deposition Modules:
○Evaporator: Metal-melting crucible + super-heater (1500°C+).
○Sputter Tool: Ion gun + rotating metal target.
○CVD Reactor: Gas injectors + radio-frequency "zapper".
●Support Systems:
○Wafer spinner (rotates at 500 RPM for uniform films).
○Thickness monitor (lasers measure coatings within 1 atom’s width).
Why It Matters
●Tech Foundation: Your smartphone uses 50+ deposited layers for processors/memory.
●Performance Secrets: Thinner films = faster chips (e.g., 3nm iPhone processors).
●Beyond Chips: Also used for solar panels (light-absorbing films) and camera sensors.
This station is different from the above film deposition. Here are examples to help understand:
Step 5: Film Deposition → At this step, you typically deposit a layer of HfO₂ or SiO₂ to serve as the gate dielectric.
Step 6: Hardmask Deposition → To enable precise etching in the next step (Gate Patterning) without damaging the gate dielectric layer, a hardmask such as SiN or amorphous carbon is deposited on top as a protective etch-resistant layer.
Etch Stop/ Hardmask Deposition is a must station before photoresist coating in the next station- Gate Patterning, because:
●Protects the Underlying Layers During Etching: Gate stacks (e.g., High-k dielectric + Metal Gate) are composed of thin, delicate materials.During gate etching, aggressive plasma chemistries (Cl₂, HBr, etc.) are used to achieve high anisotropy and vertical sidewalls. A hardmask layer (e.g., SiN, SiON,amorphous carbon) serves as a robust etch barrier, shielding the underlying layers (e.g., the channel, isolation oxides) from over-etch damage.
●Provides Pattern Transfer Accuracy: Photoresists alone are often too soft or too thin to withstand long plasma etch steps, especially for Narrow gates (sub-20 nm) & Multi-layer gate stacks
The gate pattern is first transferred from the photoresist into the hardmask, which then guides the etching of the actual gate material — this improves critical dimension (CD) control, profile precision, and line edge roughness (LER).
●Enables Etch Selectivity: Modern gate stacks include materials like HfO₂, TiN, TaN, or polysilicon.The hardmask material is selected to have high etch selectivity relative to these materials, enablin Clean stopping points (etch stop) and Reduced risk of punch-through into the substrate.
●Critical for Advanced Nodes (FinFET, GAA, etc.): In technologies like FinFET or Gate-All-Around (GAA), gate patterning happens over 3D structures, and precision is critical.
A hardmask ensures uniform etching across varied topographies and reduces erosion or footing effects.
Process Flow
●Wafer Cleaning:Remove particles, organics, moisture before deposition
●Etch Stop Layer Deposition: Deposit thin films (e.g., SiN, Al₂O₃) to define etch depth
●Hardmask Deposition: Apply robust mask layer (e.g., amorphous carbon, SiON, TiN)
●Post-deposition Bake/Anneal: Optional thermal step to improve adhesion and film quality
Core Principle
Chemicals dissolve exposed bare metal.
The protective "resist" layer shields the metal you want to keep (like a stencil).
Control depth by time, temperature, and chemical strength.
Key Consumables
●Etch Stop Films: Si₃N₄, Al₂O₃, SiCN
●Hardmask Films: Amorphous carbon, TiN, SiON
●Precursors: SiH₄, NH₃, TDMAS, TEOS (for CVD/ALD)
●Carrier Gases: Ar, N₂, H₂
Etching Machine: The star! Has spray nozzles, conveyor belt, heaters, chemical tanks, and fume exhaust. This is where the metal dissolves.
Cleaners: Tanks or ultrasonic baths for prep and final wash.
Coater/Laminator: Applies the photoresist "stencil".
UV Exposure Unit: Hardens resist using light & a pattern mask.
Developer/Stripper Tanks: Remove specific resist layers.
Rinse Stations: Multiple tanks for thorough washing.
Drying System: Air knives or ovens to dry parts.
Waste Treatment: Tanks to handle used chemicals safely.
Input: Wafer with gate dielectric and hardmask layers deposited
Output: Wafer with patterned gate stack (photoresist removed)
Gate Patterning is to precisely define the transistor gate structure by transferring a lithographic pattern onto the substrate, followed by material deposition/ removal to form functional gates critical to device performance.
Purpose:
Gate Patterning defines the physical structure and critical dimensions (CD) of the transistor gate, which controls channel conductivity and switching behavior. This step is crucial for achieving device performance, speed, and scaling targets.
Process Flow
●Substrate Cleaning
○Removes particles, organic residues, and moisture from wafer surface
○Methods: Solvent clean (acetone/IPA), plasma dry clean, or SC-1 clean
●Photoresist Coating
Apply a layer of photoresist via spin coating
○Example: Chemically amplified resist (e.g., ARF resist for 193 nm lithography)
○Bake: Soft bake (90–130°C) to remove solvents and improve adhesion
●Exposure (Pattern Transfer)
○Transfer gate pattern from photomask using:
■Immersion Lithography (193i) or EUV Lithography (13.5 nm) for advanced nodes
○Tools: ASML stepper/scanne
○Critical Parameters: Dose, focus, illumination settings
●Post-Exposure Bake (PEB)
○Stabilizes the photoacid generator and improves CD uniformity
●Development:Develop the photoresist to reveal gate patter
●Hardmask Etch (if applicable)
○Transfer resist pattern into the hardmask (e.g., SiN, amorphous carbon)
○Etch Chemistry: CH₄/O₂, CF₄, or Cl₂ plasm
○Ensures photoresist is not directly exposed to aggressive gate etch
●Gate Stack Etching
○Etch through gate electrode layers (e.g., TiN, polysilicon, or metal stacks)
○Must stop precisely on the gate dielectric (e.g., HfO₂)
○Etch Types:
■Dry Etch: High-selectivity plasma etch
■Goals: Vertical sidewalls, minimal CD loss, no footing
●Resist Strip / Ashing
○Remove residual photoresist and polymers
○Methods: O₂ plasma ashing or solvent strip (e.g., NMP at 70°C)
●Post-Etch Cleaning
○Remove etch by-products and residues
○Chemistry: Diluted HF, SC-2 clean
Core Principles
●Pattern transfer via lithography and plasma etch
●Maintain CD accuracy, vertical profiles, and low line edge roughness (LER)
●Protect sensitive gate dielectric from plasma or ion damage
Key Consumables
●Etching Chemicals:
○FeCl₃: For Cu/Al etching; concentration-dependent kinetics .
○Acids/Alkalis: H₂SO₄, HNO₃, or NaOH for specific metals .
●Photoresists:
○Positive Resists (e.g., PMMA): Degrade upon exposure for higher resolution .
○Chemically Amplified Resists: Use photoacid generators (PAGs) for sensitivity enhancement .
●Developers/Strippers:
○Alkaline solutions (e.g., TMAH) for positive resists; solvents for lift-off .
●Photomasks:
○Binary: Chrome/quartz plates for optical lithography; wear reduces pattern fidelity .
○Grayscale: For 3D structures; susceptible to defects .
●Spray Nozzles/Filters:
○Silicon carbide nozzles resist chemical corrosion; clogging from precipitates (e.g., Fe(OH)₃) requires filtration .
Main Equipment
●Coater/Developer Tracks:
○Spin-coaters with rpm/temperature control for uniform resist layers .
●Lithography Systems:
○E-beam Writers: For nanoscale gate patterns (e.g., <20 nm) .
○UV Exposure Units: Mercury lamps or lasers (e.g., KrF/248 nm) .
●Etching Machines:
○Wet Etchers: Spray-chamber systems with:
■Temperature-controlled tanks (45–50°C for FeCl₃) .
■Conveyor belts for throughput .
○Dry Etchers: Reactive-ion etchers (RIE) for anisotropic profiles .
●Metallization Tools:
○Sputtering/Evaporators for gate metal deposition (e.g., Pd/Au) .
●Ancillary Systems:
○Rinse Stations: Multi-tank setups for cascaded cleaning .
○Waste Treatment:
◼Electrolysis units for Cu recovery from spent etchants .
◼MVR evaporators for NH₄Cl concentration .
●Process Controllers:
○PID systems regulate temperature/etch rates (e.g., Kp=2000%, Ti=180s)
Input: Wafer with defined gate structures
Output: Wafer with precisely doped Source/Drain regions (NMOS/PMOS)
Purpose:
Ion implantation introduces dopant ions (e.g., boron, phosphorus, arsenic) into specific regions of the silicon wafer to alter electrical properties, forming the source and drain of transistors. This process controls the type (n-type or p-type) and concentration of carriers in semiconductor regions.
Process Description:
●Wafer Preparation
○Wafer is aligned and mounted in a vacuum chamber.
○Photoresist or hardmask patterns may protect regions not to be doped.
●Dopant Selection
○n-type (NMOS): Phosphorus (P), Arsenic (As)
○p-type (PMOS): Boron (B), BF₂
●Ion Acceleration & Beam Generation
○Dopant atoms are ionized and accelerated through an electric field.
○Energy range: 10 keV to several MeV depending on depth needed.
○Dose: Typically 101310^{13}1013 to 1016 ions/cm210^{16} \, \text{ions/cm}^21016ions/cm2
●Implantation Through Openings
○High-energy ions penetrate silicon in exposed areas (gate edges).
○Beam rastering ensures uniform dose over the wafer.
○Tilt angles may be used to minimize channeling effects.
●Depth Control
○Adjusting implant energy determines depth (shallow for source/drain extensions, deeper for well formation).
○Advanced nodes use multiple implantation steps with varying doses/energies.
Key Equipment:
●Ion Implanter (e.g., Axcelis, Applied Materials)
●Mass filter to purify ion species
Input: Wafer with doped source/drain regions (post-ion implantation)
Output: Wafer with electrically activated dopants and repaired crystal lattice
Purpose:
●Activate dopants by moving them into substitutional lattice sites where they can contribute free carriers
●Repair lattice damage caused by ion implantation
●Minimize dopant diffusion to preserve sharp junctions and maintain device performance
Principle:
The principle of RTA is based on solid-state diffusion and thermal activation:
●At elevated temperatures, implantation-induced crystal defects are healed, and dopants gain sufficient energy to become electrically active by occupying substitutional lattice sites.
●The process uses rapid heating and cooling to reduce thermal diffusion, thus maintaining tight dopant profiles essential for nanoscale transistors.
Process Description:
●Wafer Loading
Wafers are loaded into a Rapid Thermal Processing (RTP) chamber under an inert atmosphere (e.g., nitrogen or argon) to avoid oxidation.
●Rapid Heating
○Wafers are heated using high-intensity halogen lamps, reaching temperatures of 900–1100°C at ramp rates of 100–200°C/s.
●Annealing
○Wafers are held at peak temperature for 1–30 seconds, depending on device requirements, to activate dopants and repair lattice damage.
●Cooling
○Rapid cooldown prevents unwanted dopant diffusion and thermal stress, usually achieved in less than 10 seconds.
Key Equipment:
●RTP tools (e.g., Applied Materials Radiance, ASM A400, Mattson Helios)
●Optical pyrometers or thermocouples for precise temperature measurement and control
Key Consumables:
●Inert Process Gases:
○High-purity Nitrogen (N₂) or Argon (Ar): Prevents oxidation and contamination
○Forming gas (N₂ + H₂ mixture): Used when hydrogen passivation is desired
●Quartz or Sapphire Wafer Holders:
○Must withstand high temperatures and maintain cleanliness
●Halogen Lamps (Tungsten-Halogen):
○Periodically replaced due to wear and efficiency drop
●Gas Purifiers / Filters:
○To maintain ultra-clean gas lines and avoid contamination
●Temperature Sensors (e.g., Thermocouples, Pyrometers):
○Critical for closed-loop temperature feedback and control
Input: Wafer with doped source/drain and gate regions (post-RTA)
Output: Wafer with low-resistance metal silicide formed at contact regions (source, drain, gate)
Purpose:
Silicide formation reduces the electrical resistance between the polysilicon gate and the metal interconnects, as well as between source/drain regions and metal contacts. This step is crucial for maintaining high switching speeds and low power consumption in modern transistors.
Principle:
The process relies on a solid-state chemical reaction between a deposited transition metal (such as Ni, Ti, or Co) and silicon in localized regions (gate, source/drain). Upon heating, a metal silicide (e.g., NiSi, TiSi₂, or CoSi₂) forms selectively where metal contacts silicon.Silicide formation improves conductivity without shorting other regions due to the self-aligned nature of the process.
Process Flow:
●Metal Deposition
○Deposit a thin metal layer (e.g., 10–30 nm Ni, Ti, or Co) over the entire wafer via physical vapor deposition (PVD) or sputtering.
●Rapid Thermal Annealing (First Step)
○Heat wafer to initiate the reaction between metal and exposed silicon to form metal-rich silicide phases.
○Non-silicon regions (e.g., oxide or nitride areas) do not react with metal → self-aligned process.
●Selective Etching
○Remove unreacted metal from dielectric areas using wet chemical etchants (e.g., H₂SO₄ + H₂O₂ for Ni).
○Leaves silicide only at source, drain, and gate contact regions.
●Second Annealing Step (Optional)
○Optional RTA step to convert the initial metal-rich silicide into a more stable low-resistivity phase (e.g., NiSi instead of Ni₂Si).
Key Equipment
●PVD/Sputtering Tools (e.g., Applied Materials Endura, ULVAC)
●Rapid Thermal Annealing (RTA) Systems
●Wet Bench or Spin Spray Etcher for selective metal removal
Key Consumables:
●High-purity Metals: Ni, Ti, or Co sputtering targets
●Inert Gases: Argon (Ar) for sputtering
●Wet Etchants:
○SC1 (H₂O₂/NH₄OH/H₂O) or Sulfuric-peroxide mix (H₂SO₄ + H₂O₂)
○Specialized etchants for selective metal removal without attacking silicide
●Quartz Carrier/Boat for RTA
●Wafer Cleaning Chemicals (e.g., IPA, DI water, Megasonic solutions)
CMP is the final step of FEOL and a key enabler of multilayer integration. Without CMP, modern multi-level interconnects and nanometer-scale lithography would not be feasible.
Input: Wafer with uneven surface due to previous deposition, etching, or silicide formation
Output: Wafer with a highly planarized surface, ready for precise lithography or further stacking
Purpose:
Chemical Mechanical Polishing (CMP) is used to planarize the wafer surface by removing topographical variations caused by prior processing steps. It enables successful multi-layer stacking, accurate lithography alignment, and reliable metal interconnect formation in the next stages.
Principle:
CMP combines mechanical abrasion (via a rotating polishing pad and downforce pressure) with chemical etching (via reactive slurry) to remove material in a controlled and uniform manner.
Different slurries are designed to selectively polish oxide, metal, or nitride materials while stopping at specific layers.
Process Flow:
1.Slurry Application:
○Dispense a chemically reactive slurry on the polishing pad.
○The slurry contains abrasive particles (e.g., silica, alumina) and chemical agents tailored for target materials.
2.Polishing:
○Wafer is mounted on a rotating carrier head.
○Both the pad and the wafer rotate while pressure is applied.
○The combination of friction and chemical reaction removes material and planarizes the surface.
3.End Point Detection:
○Real-time sensors monitor thickness or surface uniformity (e.g., optical or motor torque feedback).
○The process stops once the desired flatness or thickness is reached.
4.Post-CMP Cleaning:
○Essential to remove slurry residues, particles, and contaminants.
○Typically done with brush scrubbing, megasonic cleaning, or chemical rinse (SC1).
Example Applications:
●Planarization of:
○STI regions (Shallow Trench Isolation CMP)
○ILD layers (Interlayer Dielectrics before metal)
○Metal CMP (e.g., Cu, W after electroplating)
○Poly CMP (after poly-silicon deposition)
Key Equipment:
●CMP Tool (e.g., Applied Materials Reflexion, Ebara Frex, TEL Mirra)
●Post-CMP Cleaning Module (integrated or standalone)
Key Consumables:
●CMP Slurry:
○Oxide CMP: Silica-based slurries (e.g., Cabot SS-12)
○Metal CMP: Slurries with oxidizers (H₂O₂, ferric nitrate) and corrosion inhibitors
○Barrier CMP: Specially tuned for materials like TaN or TiN
●Polishing Pads: Polyurethane pads with specific porosity and hardness
●DI Water and Cleaning Chemicals: For post-CMP cleaning
●Pad Conditioners: Diamond disk used to roughen the pad during operation to maintain efficiency
Contact Hole Etch marks the beginning of MEOL, ensuring that metal contacts can be precisely formed to connect the transistor terminals with minimal parasitic resistance or leakage.
Input: Planarized wafer with completed transistor structures and dielectric layers
Output: Wafer with precisely etched contact holes exposing source, drain, and gate terminals for metal connection
Purpose:
To create vertical openings (contact holes) through the interlayer dielectric (ILD) to access the transistor terminals—source, drain, and gate—for subsequent metal plug filling and electrical connectivity.
Principle:
Plasma (dry) etching is used to selectively remove dielectric material (e.g., SiO₂, SiCN) with anisotropic precision, forming deep, narrow, high-aspect-ratio contact holes. A hardmask or photoresist protects other areas during etching.
Process Flow:
●Lithography Patterning:
○Apply and pattern a photoresist or hardmask layer to define contact hole locations.
●Etching of Dielectric (ILD):
○Use reactive ion etching (RIE) or ICP (Inductively Coupled Plasma) etching with fluorine-based gases (e.g., CF₄, CHF₃, C₄F₈) to remove ILD and expose the underlying transistor contact regions.
○For CA (Contact to Active) and CB (Contact to Gate), dual-layer ILDs may be etched step-by-step.
●Etch Stop Layer (Optional):
○A SiN or SiCN etch-stop layer may be used to avoid over-etching into the device layers and maintain contact integrity.
●Resist Removal & Cleaning:
○Remove remaining resist using plasma ashing or wet strip, then perform wet cleaning (e.g., diluted HF or SC1) to eliminate residues and open up clean via surfaces.
Key Equipment:
●Etching System:
○Lam Research, TEL, Applied Materials ICP/RIE tools
●Wet Bench/Cleaning Stations:
○For resist removal and post-etch clean
Key Consumables:
●Photoresist & Hardmask Materials:
○For patterning protection during etching
●Etching Gases:
○Fluorocarbon gases (CF₄, CHF₃, C₄F₈), Ar, O₂
●Etch Stop Layer Materials (optional):
○SiN, SiCN
●Post-Etch Cleaning Chemicals:
○DI water, diluted HF, SC1 (NH₄OH + H₂O₂ + H₂O)
Example Applications:
●CA Contact Hole Etch: Connects to source/drain diffusion region
●CB Contact Hole Etch: Connects to polysilicon gate
Barrier Layer Deposition is a critical MEOL step ensuring reliable and stable contact formation by blocking metal diffusion, preserving low resistance, and enabling tight design rules in advanced semiconductor nodes.
Input: Wafer with etched contact holes exposing the transistor terminals (source, drain, gate)
Output: Wafer with contact holes conformally coated with a barrier layer (e.g., TiN, TaN), ready for metal filling
Purpose:
To deposit a thin, conformal barrier layer inside the contact holes to:
●Prevent metal diffusion (e.g., tungsten, copper) into the surrounding dielectric or silicon
●Ensure good adhesion between the contact metal and underlying layers
●Enhance reliability and maintain low contact resistance
Principle:
Barrier materials such as Titanium Nitride (TiN) or Tantalum Nitride (TaN) are deposited using conformal techniques like:
●PVD (Physical Vapor Deposition) – sputtering for relatively simple structures
●CVD (Chemical Vapor Deposition) – for better step coverage
●ALD (Atomic Layer Deposition) – for high aspect ratio contact holes requiring atomic-level thickness control
These techniques ensure a uniform layer on the sidewalls and bottom of contact holes without voids or overhangs.
Process Flow:
1.Wafer Preparation:
○Start with a cleaned wafer with defined contact holes from Step 12.
2.Barrier Layer Deposition:
○Deposit a uniform barrier film using:
■TiN via PVD or ALD (common for tungsten plugs)
■Ta/TaN via PVD (common for copper interconnects)
○Typical thickness: 5–20 nm, depending on application and tool.
3.Post-Deposition Treatment (Optional):
○Mild plasma treatment or annealing may be used to densify the film and reduce defects.
Key Equipment:
●ALD Tools: ASM, Applied Materials, Lam Research
●PVD Systems: ULVAC, AJA International, Applied Materials Endura
●CVD Reactors: For TiN CVD, if conformality is needed over PVD
Key Consumables:
●Target Materials: Ti, Ta (for PVD)
●Precursor Gases:
○TiCl₄, TDMAT (Ti[N(CH₃)₂]₄) for TiN
○TaCl₅, TBTDET for TaN
●Carrier/Reactant Gases: NH₃, N₂, Ar, H₂
●Cleaning gases (for in-situ chamber clean): NF₃, O₂
Input: Wafer with etched contact holes lined with a barrier layer (e.g., TiN or TaN)
Output: Wafer with metal-filled contact holes (plugs) connecting the transistor terminals to the first metal layer (Local Interconnect M0)
Metal Fill (Contact Plug) forms the electrical bridges between the transistors and the wiring layers above. Tungsten is widely used in traditional CMOS nodes, while copper dominates advanced nodes with damascene integration. This step must ensure void-free, low-resistance, and reliable contacts in shrinking geometries.
Purpose:
To fill the contact holes with a conductive metal (typically tungsten (W) or copper (Cu)), forming reliable electrical connections between the active device areas (source/drain/gate) and the subsequent interconnect layers.
Principle:
Metal is deposited into the contact holes via:
●Chemical Vapor Deposition (CVD) – commonly used for tungsten plugs
●Electroplating (ECD) – used for copper in damascene processes
●Atomic Layer Deposition (ALD) – for conformal filling in narrow, high-aspect-ratio features
The barrier layer prevents diffusion, and a seed layer (typically of the same metal) may be required to initiate uniform metal growth.
Process Flow:
1.Pre-Cleaning (Optional):
○Clean the contact holes with plasma or wet chemistry to remove native oxides or residues.
2.Seed Layer Deposition (if Cu-based):
○Deposit a thin copper seed layer over the barrier (PVD or CVD) for plating conductivity.
3.Metal Deposition:
○For Tungsten (W) plugs:
■Use CVD W with precursors like WF₆ and H₂.
○For Copper (Cu) plugs:
■Use electrochemical deposition (ECD) to fill the holes.
4.Overburden Removal (for Damascene Cu):
○Perform CMP (Chemical Mechanical Polishing) to remove excess metal and planarize the surface.
Key Equipment:
●CVD Systems (e.g., Applied Materials Centura for W)
●Electroplating Systems (e.g., Lam Research Sabre for Cu)
●PVD Systems (for Cu seed layer)
●CMP Tools (for post-deposition planarization)
Key Consumables:
●Tungsten Precursors: WF₆ (tungsten hexafluoride), H₂, SiH₄
●Copper Electrolyte Solutions: CuSO₄, H₂SO₄, additives for leveling/wetting
●Barrier & Seed Materials: TiN, TaN, Cu
●CMP Slurries and Pads (if post-deposition polish is required)
Contact Resistance Optimization ensures that the interface between metal contacts and silicon is as conductive as possible. By combining annealing, silicide formation, and interface engineering, this step minimizes voltage drop and performance bottlenecks—especially important in high-speed and low-power applications.
Input: Wafer with metal-filled contact plugs
Output: Wafer with low-resistance, thermally stable contacts, ensuring efficient current flow from transistor terminals to interconnects
Purpose:
To reduce and stabilize the resistance at the metal-semiconductor interface (contact resistance), which is critical to device speed, power efficiency, and signal integrity—especially at nanoscale nodes.
Principle:
●Contact resistance arises due to the Schottky barrier and interfacial defects between metal plugs (e.g., W or Cu) and doped semiconductor regions.
●Optimization aims to improve carrier injection and enhance interface quality through:
○Annealing: Activates dopants and improves metal-semiconductor bonding.
○Silicide Engineering: Forms low-resistance metal silicides at the contact interface.
○Interface Modification: Using adhesion layers or dopant segregation to reduce barrier height.
Process Flow:
1.Post-Metal Fill Annealing:
○Rapid Thermal Annealing (RTA) at ~400–600 °C for a few seconds in N₂ or forming gas (H₂/N₂) atmosphere.
○Improves grain structure, lowers contact resistivity.
2.Silicide Contact Engineering (optional):
○If not done earlier, form a thin NiSi, CoSi₂, or TiSi₂ layer at the interface.
○Enhances contact uniformity and reduces resistivity.
3.Surface Treatment / Interface Tuning:
○Techniques like dopant segregation (e.g., boron spike at contact edge) to modulate Fermi level.
○Plasma treatments (e.g., H₂ or NH₃) to reduce interface states.
4.Measurement and Control:
○Use Kelvin structures or Transmission Line Models (TLM) to characterize and tune contact resistance.
Key Equipment:
●Rapid Thermal Processing (RTP) Systems (e.g., ASM A400, Applied Centura)
●Plasma Surface Treatment Tools (e.g., for H₂, N₂ pre-clean)
●Metrology Tools (e.g., 4-point probe, nano-CMM)
Key Consumables:
●Annealing Gases: N₂, H₂/N₂ (Forming gas)
●Barrier/Silicide Materials: Ti, Co, Ni (if silicide formed here)
●Surface Chemicals: HF, NH₄OH, H₂ plasma for surface prep
●Dopant Elements: Boron (B), Arsenic (As), Phosphorus (P)
Why It Matters:
●At advanced nodes (e.g., 5 nm, 3 nm), contact resistance dominates total series resistance.
●Optimization improves:
○Drive current (Ion)
○Switching speed
○Power efficiency
○Yield and reliability
Input: Wafer with metal contact plugs and exposed surfaces
Output: Wafer covered with a dielectric insulating layer between metal layers
Goal:
Deposit an insulating dielectric layer to electrically isolate different metal interconnect layers, preventing short circuits and minimizing parasitic capacitance.
Process Flow:
● Surface Preparation: Clean and prepare the wafer surface for uniform dielectric deposition.
● Dielectric Deposition: Deposit a dielectric film (e.g., SiO₂, SiN, low-k materials) using methods such as Chemical Vapor Deposition (CVD), Plasma Enhanced CVD (PECVD), or Spin-On Dielectrics (SOD).
● Pre-Cure Treatment: Some dielectrics require pre-curing to improve film quality.
● Post-Deposition Annealing: Anneal the wafer to densify the dielectric and improve electrical and mechanical properties.
Core Principle:
Dielectric materials with high electrical resistivity and low dielectric constant (k) are deposited to insulate metal layers and reduce parasitic capacitance, thereby improving circuit speed and reliability.
Key Consumables:
●Dielectric precursor gases (e.g., silane (SiH₄), nitrous oxide (N₂O), ammonia (NH₃))
●Low-k dielectric materials (e.g., organosilicate glass, fluorinated silicates)
●Cleaning chemicals for surface prep (e.g., solvents, plasma gases)
Main Equipment:
●CVD or PECVD reactors for dielectric film deposition
●Spin coaters (for spin-on dielectrics)
●Annealing furnaces or rapid thermal processing (RTP) systems
●Cleaning and plasma treatment systems
Input: Wafer with non-planar dielectric and metal layers after ILD deposition
Output: Wafer surface polished to a smooth, flat, and planar state, ready for subsequent lithography and metallization steps
Goal:
Achieve a globally planar surface by removing excess dielectric and metal, ensuring uniformity across the wafer for precise photolithography and reliable layer stacking in multi-level interconnects.
Process Flow:
● Preparation: Mount the wafer on a polishing carrier.
● Polishing: Use a CMP tool combining mechanical abrasion (with a polishing pad) and chemical etching (via slurry) to remove surface irregularities.
● Slurry: The slurry contains abrasive particles and reactive chemicals tailored to selectively polish dielectric or metal layers.
● End-Point Detection: Monitor wafer surface to determine when desired flatness is reached and avoid over-polishing.
● Cleaning: Thoroughly clean the wafer post-polishing to remove slurry residues and particles.
Core Principle:
CMP simultaneously uses mechanical friction and chemical reactions to remove materials, leveling the wafer surface by selectively polishing high points faster than low points, resulting in an ultra-flat topography critical for device performance.
Key Consumables:
●Polishing pads (different hardness and textures depending on materials)
●CMP slurry (abrasive particles like silica or alumina, chemicals like oxidizers and pH adjusters)
●Cleaning chemicals and ultra-pure water
Main Equipment:
●CMP polishing machines with carrier heads and polishing platens
●End-point detection systems (optical or motor current monitoring)
●Automated cleaning stations
Input: Wafer with planarized metal interconnect layers from CMP
Output: Wafer coated with an insulating dielectric layer separating metal layers
Goal:
Deposit a uniform dielectric layer that electrically isolates different metal interconnect layers, preventing short circuits and crosstalk between signal lines.
Process Flow:
●Surface Preparation: Clean wafer surface to ensure good adhesion.
●Deposition: Apply dielectric material using techniques such as Chemical Vapor Deposition (CVD), Plasma-Enhanced CVD (PECVD), or Atomic Layer Deposition (ALD).
●Thickness Control: Precisely control thickness to meet electrical and mechanical specifications.
●Post-Deposition Treatment: May include annealing to improve film quality and reduce defects.
Core Principle:
Form a high-quality insulating film (e.g., silicon dioxide (SiO₂), silicon nitride (Si₃N₄), or low-k dielectrics) on the wafer surface to electrically separate conductive metal layers and maintain signal integrity.
Key Consumables:
●Precursor gases (e.g., silane, oxygen, nitrogen) for CVD
●Plasma gases for PECVD
●High-purity inert gases
●Cleaning chemicals
Main Equipment:
●CVD or PECVD reactors
●ALD tools (for ultra-thin, conformal layers)
●Wafer cleaning stations
Input: Wafer coated with dielectric layer
Output: Wafer with patterned trenches and vias etched into the dielectric, ready for metal filling
Goal:
Create precise trenches and vias in the dielectric layer to form the metal interconnect network for electrical connections between different layers.
Process Flow:
●Photoresist Coating: Apply a photoresist layer on the dielectric surface.
●Exposure & Development: Use photolithography to define the pattern for trenches and vias.
●Etching:
○First, etch vias down to the lower metal layer contact points.
○Then etch trenches horizontally to form wiring channels.
●Photoresist Removal: Strip away the remaining photoresist after etching.
●Cleaning: Clean wafer to remove etch residues.
Core Principle:
Use a two-step etch process to form vertical (vias) and horizontal (trenches) features simultaneously in the dielectric layer, enabling efficient metal interconnect routing with fewer process steps.
Input wafer with etched trench/via patterns; output wafer conformal barrier layer (e.g., TaN) and seed layer (e.g., Cu), preparing for electroplating.
Input: Wafer with etched trenches and vias (Dual Damascene pattern)
Output: Wafer coated with conformal barrier and seed layers inside trenches and vias
Goal:
Deposit thin, uniform barrier and seed layers to prevent metal diffusion and enable subsequent electroplating of copper interconnects.
Process Flow:
●Barrier Layer Deposition: Deposit a thin barrier layer (e.g., TaN, TiN) conformally inside trenches and vias to prevent copper diffusion into the dielectric.
●Seed Layer Deposition: Deposit a thin copper seed layer on top of the barrier layer to provide a conductive base for electroplating.
Core Principle:
Physical vapor deposition (PVD) or atomic layer deposition (ALD) methods are typically used to achieve conformal coverage of barrier and seed layers within the high-aspect-ratio features.
Key Consumables:
●Target materials (Ta, Ti, Cu) for sputtering
●Process gases (Ar, N₂, etc.) for sputtering environment
Main Equipment:
●Sputtering or ALD deposition systems
●Vacuum chambers with precise thickness control
Input: Wafer coated with barrier and seed layers inside trenches and vias
Output: Wafer with trenches and vias filled with electroplated copper
Goal:
Fill the patterned trenches and vias with copper to form low-resistance metal interconnects.
Process Flow:
●Place the wafer in an electroplating bath containing a copper electrolyte solution.
●Apply an electric current to deposit copper selectively onto the seed layer inside the trenches and vias.
●Control plating parameters to ensure void-free and uniform copper fill.
Core Principle:
Electrochemical deposition uses the reduction of copper ions from the electrolyte onto the conductive seed layer under applied current, enabling precise metal filling.
Key Consumables:
●Copper electrolyte solution (containing copper sulfate, sulfuric acid, additives)
●Deionized water for rinsing
Main Equipment:
●Electroplating tool with wafer holder and electrical contacts
●Filtration and chemical management systems for electrolyte bath
No. 17 CMP Planarization and No. 22 CMP Planarization are indeed both CMP steps, but they are not exactly the same station. Here's why:
●No. 17 CMP is typically performed after ILD (Interlayer Dielectric) deposition during the MEOL stage, to planarize the dielectric and prepare the surface for subsequent BEOL metallization layers.
●No. 22 CMP is performed after Cu Electroplating during the BEOL stage, to remove excess copper and polish the metal interconnect layers, creating a smooth and flat surface for stacking more metal/dielectric layers.
In summary:
Both are CMP processes, but they target different materials and happen at different manufacturing stages — one for planarizing dielectric layers (ILD) and the other for planarizing metal layers (Cu interconnects).
Input: Wafer with overfilled copper metal features after electroplating
Output: Wafer surface polished to a flat, smooth finish, exposing copper interconnects and removing excess metal
Goal:
Achieve a globally planar surface by removing excess copper and dielectric materials, enabling subsequent layer stacking with precise alignment.
Process Flow:
●Mount the wafer on a rotating platen with a polishing pad.
●Apply a slurry containing abrasive particles and chemicals that selectively remove copper and dielectric materials.
●Control pressure, speed, and slurry flow for uniform material removal and minimal defects.
●Rinse and dry the wafer after polishing.
Core Principle:
CMP (Chemical Mechanical Polishing) combines mechanical abrasion with chemical etching to achieve smooth, planar surfaces critical for multi-layer device fabrication.
Key Consumables:
●CMP slurry (abrasive + reactive chemicals)
●Polishing pads
●Deionized water for cleaning
Main Equipment:
●CMP polishing tool with adjustable pressure, speed, and slurry delivery
●Cleaning stations for post-CMP wafer rinsing
Goal:
Build multiple layers of metal interconnects to electrically connect transistors and other components, enabling complex integrated circuits.
Input:
Wafer with planarized metal and dielectric layers from previous metallization steps.
Output:
Wafer with multiple stacked metal layers (M1, M2, … Mn) interconnected through vias, ready for further processing.
Process Flow:
● Dielectric Layer Deposition: Deposit inter-metal dielectric (IMD) to insulate metal layers.
● Photolithography & Etching: Pattern trenches and vias in the dielectric to define the metal wiring paths and inter-layer connections.
● Barrier/Seed Layer Deposition: Deposit barrier and seed layers to prepare for metal filling and prevent diffusion.
● Metal Deposition: Fill patterned trenches and vias with metal (usually copper) by electroplating or chemical vapor deposition (CVD).
● CMP Planarization: Polish the wafer surface to remove excess metal and achieve a flat surface.
● Repeat: Repeat steps 1–5 for each additional metal layer until the required number of metal layers is achieved.
Principle:
Metal layers and dielectric layers are alternately deposited and patterned to form vertical and horizontal interconnects. The vias connect each metal layer vertically, enabling complex routing of electrical signals and power.
Key Consumables:
●Dielectric materials (e.g., SiO₂, low-k dielectrics)
●Photolithography chemicals (photoresists, developers)
●Barrier metals (e.g., TaN)
●Seed metals (e.g., Cu)
●Electroplating chemicals (copper sulfate solution)
●CMP slurries and pads
Main Equipment:
●Deposition tools (CVD, PECVD, sputtering)
●Lithography tools
●Etching systems
●Electroplating systems
●CMP polishing machines
Input final-metal-layer wafer, output wafer with SiN/SiO₂ passivation (0.5-1μm)
Goal:
Protect the final metal interconnect layers and the overall chip surface from environmental damage, contamination, and mechanical stress.
Input:
Wafer with completed multi-level metal interconnects and planarized dielectric surface.
Output:
Wafer coated with a protective passivation layer, typically silicon nitride (SiN) or silicon dioxide (SiO₂).
Process Flow:
● Surface Preparation: Clean wafer surface to ensure good adhesion of the passivation layer.
● Passivation Layer Deposition: Deposit a thin, uniform protective layer using techniques such as Plasma Enhanced Chemical Vapor Deposition (PECVD) or Low Pressure Chemical Vapor Deposition (LPCVD).
● Patterning (Optional): Open contact windows or bonding pads in the passivation layer using photolithography and etching if needed for subsequent packaging steps.
Principle:
The passivation layer acts as a physical barrier to prevent moisture, contaminants, and particles from reaching and damaging the delicate metal and dielectric layers underneath, enhancing device reliability and longevity.
Key Consumables:
●Passivation gases/precursors (e.g., silane, ammonia, nitrogen)
●Photolithography chemicals (if patterning is needed)
●Etchants for opening windows
Main Equipment:
●PECVD or LPCVD deposition systems
●Lithography and etching equipment (if patterning)
●Cleaning stations
Goal:
To vertically stack multiple semiconductor dies or layers, enabling higher device density, improved performance, and enhanced functionality in a smaller footprint.
Input:
Wafer with completed front-end and back-end processing, often thinned and passivated.
Output:
Stacked dies connected vertically via Through-Silicon Vias (TSVs), micro-bumps, or other interconnect technologies, forming a 3D integrated structure.
Process Flow:
● Wafer Thinning: Thin the wafer to reduce thickness for easier vertical stacking and heat dissipation.
● Through-Silicon Via (TSV) Formation: Etch vertical holes through the silicon wafer and fill them with conductive materials (e.g., copper) to create electrical connections between stacked layers.
● Die/Layer Bonding: Align and bond multiple wafers or dies using techniques such as wafer-to-wafer, die-to-wafer, or die-to-die bonding.
● Interconnect Formation: Form micro-bumps or other interconnects to electrically connect the stacked dies.
● Testing and Inspection: Verify electrical connectivity and mechanical integrity of the 3D stack.
Principle:
By stacking semiconductor components vertically and connecting them with TSVs, 3D integration reduces interconnect length, lowers parasitic capacitance, and improves overall chip speed and energy efficiency, while enabling heterogeneous integration of different technologies.
Key Consumables:
●Etchants and chemicals for TSV etching
●Conductive materials for TSV filling (e.g., copper, tungsten)
●Adhesives or bonding materials
●Cleaning agents
Main Equipment:
●Wafer thinning/polishing tools
●Deep reactive ion etching (DRIE) systems for TSV creation
●Chemical vapor deposition (CVD) or electroplating tools for TSV filling
●Precision alignment and bonding machines
●Inspection and test equipment
Goal:
To create additional metal routing layers on the wafer/die surface, allowing flexible input/output (I/O) pad arrangements and improved electrical connectivity for advanced packaging.
Input:
Wafer or die with completed back-end metal layers and passivation layers.
Output:
Wafer or die with patterned redistribution metal layers and vias, enabling optimized I/O layout for chip packaging and interconnection.
Process Flow:
● Passivation Opening: Etch openings in the passivation layer to expose underlying metal pads for RDL connection.
● Dielectric Layer Deposition: Deposit a dielectric (insulating) layer over the wafer to isolate the redistribution metal.
● Photolithography & Patterning: Apply photoresist, expose, and develop the desired RDL pattern.
● Metal Deposition: Deposit thin metal layers (e.g., copper or aluminum) by sputtering, electroplating, or evaporation to form the redistribution traces.
● Etching: Remove excess metal outside the RDL pattern areas.
● Via Formation: Create vias (holes) in the dielectric to connect RDL layers to underlying metal pads or other RDL layers (if multilayer RDL).
● Curing and Final Cleaning: Cure the dielectric and metal layers and clean the wafer/die surface.
Principle:
RDL extends or redistributes the I/O pads from their original positions on the die to locations better suited for packaging and external connections, facilitating smaller package sizes, finer pitch, and improved electrical performance.
Key Consumables:
●Dielectric materials (polyimide, benzocyclobutene (BCB), or other insulators)
●Photoresists and developers
●Metals for deposition (copper, aluminum)
●Etchants for dielectric and metal patterning
●Cleaning chemicals
Main Equipment:
●Photolithography systems
●Metal deposition tools (sputtering, electroplating)
●Etching equipment (wet or dry etching)
●Curing ovens or UV curing systems
●Inspection and metrology tools
Goal:
To electrically test each individual die on a completed wafer to identify functional and defective chips before further processing.
Input:
Completed wafer with fabricated devices, prior to dicing.
Output:
Wafer with tested chips, where functional dies are marked (e.g., ink dot or electronically recorded) and defective dies are identified.
Process Flow:
● Probe Card Alignment: Align the probe card contacts with the electrical pads of each die on the wafer.
● Electrical Testing: Apply test signals and measure the electrical responses of each die using Automated Test Equipment (ATE).
● Defect Identification: Analyze test results to classify dies as functional or defective.
● Marking: Mark functional dies with an ink dot or store test data electronically for downstream sorting and packaging.
● Data Logging: Record test outcomes for yield analysis and quality control.
Principle:
Probe testing verifies the electrical integrity and functionality of semiconductor devices at the wafer level, enabling early detection of defects before wafer dicing and packaging.
Key Consumables:
●Probe cards
●Test interface materials (e.g., probe needles)
●Cleaning agents for probe cards and wafers
Main Equipment:
●Automated Test Equipment (ATE)
●Probe stations with precision alignment systems
●Data acquisition and analysis software
Goal:
To reduce the wafer thickness to the desired level for improved mechanical flexibility, thermal performance, and compatibility with packaging requirements.
Input:
Full-thickness semiconductor wafer, typically after wafer sort (CP test).
Output:
Thinned wafer with uniform thickness, ready for dicing and further packaging steps.
Process Flow:
● Mounting: Attach the wafer onto a carrier or adhesive tape to securely hold it during grinding.
● Coarse Grinding: Use a grinding wheel or abrasive blade to remove the bulk of the wafer thickness quickly.
● Fine Grinding / Polishing: Perform a finer grinding step to achieve the target thickness and smooth surface finish, reducing surface damage and stress.
● Cleaning: Thoroughly clean the wafer to remove grinding debris, particles, and contaminants.
Principle:
Backgrinding is a mechanical abrasion process that removes material from the wafer backside to thin it down while maintaining wafer integrity.
Key Consumables:
●Grinding wheels or abrasive discs
●Carrier tape or adhesive film
●Cleaning solvents and chemicals
Main Equipment:
●Wafer backgrinders (coarse and fine grinding capability)
●Cleaning stations
●Handling tools for wafer mounting and demounting
Goal:
To separate the thinned wafer into individual semiconductor dies (chips) for packaging and testing.
Input:
Thinned semiconductor wafer, typically after backgrinding and inspection.
Output:
Individual semiconductor dies separated from the wafer, still attached to the dicing tape or carrier.
Process Flow:
● Mounting: Secure the wafer on a dicing tape stretched over a frame to hold the dies during cutting.
● Sawing / Cutting: Use a high-precision dicing saw or laser to cut along the scribe lines (streets) between the dies.
● Debris Removal: Remove cutting debris and particles from the wafer surface.
● Inspection: Check for die integrity and dicing quality to avoid damage.
Principle:
Dicing mechanically separates the wafer into discrete dies by cutting through the silicon along predefined streets, minimizing damage to active areas.
Key Consumables:
●Dicing blades or laser sources
●Dicing tape and frames
●Cleaning solvents and fluids
Main Equipment:
●Wafer dicing saws or laser dicing systems
●Tape mounting and handling tools
●Cleaning and inspection stations
Goal:
To securely attach individual semiconductor dies onto package substrates or lead frames, establishing mechanical stability and initial electrical pathways.
Input:
Separated semiconductor dies and package substrates or lead frames.
Output:
Packages with dies firmly bonded to substrates, ready for subsequent electrical interconnection steps.
Process Flow:
● Die Placement: Precisely pick and place dies onto the designated bonding area of the substrate or lead frame.
● Adhesive Application: Apply conductive or non-conductive adhesives (e.g., epoxy, solder paste) between the die and substrate.
● Bonding: Cure or reflow the adhesive through thermal, UV, or pressure processes to ensure strong mechanical attachment and good thermal/electrical conductivity.
● Inspection: Verify die alignment, bonding integrity, and absence of voids or misplacements.
Principle:
Die attach creates a stable physical and sometimes electrical connection between the die and package, ensuring mechanical support and heat dissipation.
Key Consumables:
●Conductive adhesives (silver-filled epoxy, solder paste) or non-conductive epoxies
●Substrates or lead frames
●Cleaning materials for bonding surfaces
Main Equipment:
●Die bonding machines (pick-and-place systems)
●Curing ovens or UV curing systems
●Inspection tools (microscopes, alignment systems)
Goal:
To establish reliable electrical connections between the semiconductor die and the package substrate or lead frame for signal transmission.
Input:
Die-attached packages with exposed bond pads.
Output:
Electrically connected dies via fine wires or solder bumps, ready for encapsulation.
Process Flow:
●Wire Bonding:
○Use thin metal wires (commonly gold (Au) or aluminum (Al)) to connect bond pads on the die to corresponding pads on the substrate or lead frame.
○Techniques include thermosonic, ultrasonic, or thermocompression bonding.
●Flip-Chip Interconnect:
○Flip the die face-down and attach it directly to the substrate using solder bumps (e.g., lead-free solder).
○Perform reflow soldering to form robust electrical and mechanical connections.
●Inspection: Check for bond integrity, wire looping, solder joint quality, and absence of shorts or opens.
Principle:
Wire bonding uses fine wires to create flexible connections, while flip-chip uses solder bumps for a more compact, high-performance interconnect, enabling higher I/O density and better electrical performance.
Key Consumables:
●Gold or aluminum bonding wires
●Solder bumps (lead-free solder alloys)
●Flux and cleaning agents
Main Equipment:
●Wire bonding machines
●Flip-chip bonders and reflow ovens
●Inspection microscopes and X-ray systems
Goal:
To protect the die and wire bonds from mechanical damage, moisture, dust, and other environmental contaminants, ensuring long-term reliability.
Input:
Die and substrate assemblies with completed electrical interconnections (wire bonded or flip-chip).
Output:
Encapsulated packages sealed with protective molding compounds.
Process Flow:
● Mold Preparation: Prepare the mold cavity and ensure cleanliness.
● Encapsulation: Inject epoxy-based molding compound (typically thermosetting plastic) into the mold cavity surrounding the die and interconnections.
● Curing: Cure the molding compound by applying heat and/or pressure to solidify and firmly encapsulate the die.
● Demolding: Remove the encapsulated package from the mold.
● Cleaning: Clean any residue or flash from the package surface.
Principle:
Encapsulation provides a durable mechanical and chemical barrier to safeguard sensitive semiconductor components, while maintaining package integrity during handling and operation.
Key Consumables:
●Epoxy molding compounds
●Release agents for molds
●Cleaning solvents
Main Equipment:
●Transfer molding machines
●Cure ovens
●Demolding stations
●Cleaning systems
Goal:
To verify the electrical functionality and performance of the fully assembled semiconductor devices, ensuring only defect-free products proceed to packaging and shipment.
Input:
Fully assembled semiconductor packages post-encapsulation and marking.
Output:
Tested semiconductor devices classified as pass or fail based on electrical criteria.
Process Flow:
● Test Program Preparation: Develop and load specific test patterns and parameters into Automated Test Equipment (ATE).
● Electrical Testing: Perform a series of tests including parametric, functional, and stress (burn-in) tests to evaluate device performance and reliability.
● Data Collection & Analysis: Collect test results, analyze for defects, and classify devices accordingly.
● Sorting: Separate passed devices from failed ones for further processing or scrap.
● Reporting: Generate quality and yield reports for process monitoring.
Principle:
The final test ensures that the semiconductor device meets design specifications and reliability standards by applying electrical stimuli and monitoring responses.
Key Consumables:
●Test sockets and probes
●Calibration standards
●Test programs and software
Main Equipment:
●Automated Test Equipment (ATE)
●Burn-in ovens (if applicable)
●Data acquisition and analysis systems
Goal:
To permanently label semiconductor devices with identification information such as part numbers, manufacturing date codes, and batch numbers for traceability and quality control.
Input:
Tested and approved semiconductor devices ready for final packaging.
Output:
Labeled semiconductor devices with clear, durable markings.
Process Flow:
● Device Placement: Secure the devices on the marking station or conveyor.
● Marking Method Selection: Choose appropriate marking technique (e.g., laser marking, inkjet printing, or dot peening) based on device type and material.
● Marking Execution: Apply the marks containing relevant information such as serial numbers, logos, date codes, or barcodes.
● Inspection: Verify the quality, accuracy, and readability of the marks.
● Cleaning (Optional): Remove any residues from the marking process if necessary.
Principle:
Marking uses precise and permanent methods to apply identifiers on device surfaces without damaging the device, ensuring traceability throughout the product lifecycle.
Key Consumables:
●Marking inks (if inkjet is used)
●Cleaning solvents (optional)
Main Equipment:
●Laser marking systems
●Inkjet printers
●Dot peen markers
●Vision inspection systems
Goal:
To securely package semiconductor devices in standardized formats (tape and reel or trays) for safe transport, automated handling, and efficient storage.
Input:
Labeled and fully tested semiconductor devices ready for shipment.
Output:
Devices packaged in reels or trays, properly sealed and labeled for shipment.
Process Flow:
● Device Feeding: Place devices into pockets of carrier tape or into designated slots in trays.
● Sealing: For tape and reel, cover the carrier tape with a protective cover tape and wind it onto reels. For trays, cover with a protective lid or film.
● Labeling: Apply shipping labels with relevant information (part number, quantity, lot number, destination).
● Inspection: Check packaging integrity, device orientation, and label accuracy.
● Final Packaging: Pack reels or trays into shipping boxes with protective materials (anti-static bags, cushioning).
Principle:
Tape and reel and tray packaging formats facilitate automated pick-and-place handling during PCB assembly, ensuring device protection and traceability throughout shipping and storage.
Key Consumables:
●Carrier tape and cover tape (for tape and reel)
●Trays and lids (for tray packaging)
●Labels and stickers
●Anti-static bags and cushioning materials
Main Equipment:
●Tape and reel packaging machines
●Tray loading systems
●Label printers and applicators
●Visual inspection systems
Semiconductor manufacturing is one of the most intricate and precise engineering feats in the modern world. From transforming raw silicon into functional chips through FEOL, MEOL, and BEOL, to preparing and validating them in ATP, the process spans over 35 critical stations and hundreds of sub-steps. This blog has walked you through the complete CMOS-based fabrication route — the mainstream method used in today’s electronics — offering clarity on the core technologies, workflows, equipment, and purposes behind each step.
Understanding this full lifecycle helps demystify how semiconductors, the foundation of all modern electronics, are made. Whether you're in the semiconductor industry, an engineering student, or just tech-curious, grasping this process gives you insight into the hidden backbone of the digital world.
FAQs
After finishing scanning these 35 stations, you may already know why semiconductors manufacturing is so struggling? This ultra long line will cost large amount of time, money, and labor. Any parts failed in one step, will not flow to a qualified final goods.
Making semiconductors takes a long time—typically 12 to 20 weeks (3 to 5 months)—because the process is incredibly complex, precise, and involves hundreds of tightly controlled steps. Here’s a breakdown of the main reasons:
Actually, Modern chips have 50 to 100 layers, and each layer requires coating with photoresist, exposure using a photomask, development, Etching, Cleaning.
This process must be repeated layer by layer, taking days to weeks depending on complexity.each of these steps must be flawless at the nanometer scale
Tools like EUV lithography scanners, ion implanters, and etchers are expensive and shared. Wafers must wait in queues between tools, adding idle time (cycle time). Fabs process 25 wafers per batch, slowing throughput further.
Intrinsic semiconductors: those with no intentional impurities (dopants), made of 100% pure semiconductor material like silicon or germanium. It’s difficult because it requires extremely high material purity, precise control, and specialized processing conditions.
We help you avoid the pitfalls to deliver the quality and value your wafer drying need, on-time and on-budget.